Reductions in the size of semiconductor devices (e.g., a metal-oxide semiconductor device) have enabled continued improvement in speed, performance, density, and cost per unit function of integrated circuits over the past few decades. In accordance with the design of a transistor and one of the inherent characteristics thereof, modulating the length of a channel region underlying a gate between a source and a drain of the transistor alters a resistance associated with the channel region, thereby affecting the performance of the transistor. More specifically, shortening the length of the channel region reduces a source-to-drain resistance of the transistor, which, assuming other parameters are maintained relatively constant, may allow for an increase in current flow between the source and drain when a sufficient voltage is applied to the gate of the transistor.
To further enhance the performance of MOS devices, stress may be introduced in the channel region of a MOS transistor to improve carrier mobility. Generally, it is desirable to induce a tensile stress in the channel region of an n-type metal-oxide-semiconductor (NMOS) device in a source-to-drain direction and to induce a compressive stress in the channel region of a p-type metal-oxide-semiconductor (PMOS) device in a source-to-drain direction.
A commonly used method for applying compressive stresses to the channel regions of PMOS devices is to grow SiGe stressors in the source and drain regions. Such a method typically includes forming a gate stack on a semiconductor substrate; forming gate spacers on sidewalls of the gate stack; forming recesses in the silicon substrate; and epitaxially growing SiGe stressors in the recesses. Since SiGe has a greater lattice constant than silicon, it applies a compressive stress to the channel region, which is located between a source SiGe stressor and a drain SiGe stressor. Similarly, SiC stressors may be formed for NMOS devices. Since SiC has a smaller lattice constant than silicon, tensile stresses may be applied to the channel regions.
Conventional stressor formation processes suffer drawbacks, however. FIG. 1 illustrates PMOS devices formed using conventional stressor formation processes. PMOS devices 2, 4 and 6 are serially connected, and SiGe stressors 8, 10, 12 and 14 are formed. SiGe stressors 8 and 14 have greater areas than SiGe stressors 10 and 12. Due to pattern-loading effects, the thicknesses of SiGe stressors 8, 10, 12 and 14 are not uniform. Particularly, SiGe stressors 8 and 14 tend to have central portions 16, which are significantly thinner than the respective edge portions. The thickness variation causes drive current degradation and thus is an undesired phenomenon.
In addition, in conventional SiGe formation processes, silicide regions on SiGe stressors are adversely affected. FIG. 2 illustrates a SiGe stressor 18 formed adjacent an N+ region 20. A silicide film 22 is formed on SiGe stressor 18 and N+ region 20 to improve contact. It has been found that in region 24, proximate an interface between SiGe stressor 18 and N+ region 20, the thickness of silicide film 22 is significantly less than in other regions.
Conventionally, to avoid the above-discussed problems, special design rules have to be followed. For example, the sizes of active regions, which include SiGe stressors, have to be limited in order to reduce pattern-loading effects. These special design rules significantly limit the flexibility of circuit design. Improved formation methods are thus needed.